EDN

Advancing FPGA design flows using Chronology’s TimingDesigner

When combined with advances in FPGA technologies that ease complex interface design efforts, Chronology's TimingDesigner can simplify design issues and provide advanced accurate control of high-speed ...
EDN

Dataflow tool replaces HDL flow

ANNAPOLIS, Md. Proclaiming a revolutionary new approach to designing reconfigurable logic, Annapolis Microsystems has announced CoreFire, which allows users to program Annapolis' FPGA-based boards by ...
Business Wire

Aldec Releases Active-HDL 10.1 with 64-bit Simulation Support

HENDERSON, Nev.--(BUSINESS WIRE)--Aldec, Inc., announces the latest release of its mixed-language FPGA design platform, Active-HDL™ 10.1. Popular with designers for more than 15 years for FPGA design ...
Design-Reuse

Mentor Graphics introduced v5.2 of its FPGA Advantage HDL design flow

Mentor Graphics introduced v5.2 of its FPGA Advantage HDL design flow for creation, management, simulation and synthesis of FPGA designs. The new version has features that improve design creation and ...
New Electronics

HES-DVM simulation acceleration flow for Microchip FPGA designs

Aldec, an expert in mixed-HDL language simulation and hardware-assisted verification for ASIC and FPGA designs, has introduced a HES-DVM simulation acceleration flow for Microchip’s PolarFire, ...
New Electronics

Aldec platform supports newest fpga devices

Electronic design verification specialist, Aldec has launched an HDL based fpga design and simulation platform that supports the newest fpga devices. According to Aldec, Active-HDL version 9.1 is a ...