Yahoo Finance

Tabula Adds SystemVerilog Support to Stylus Compiler With Verific Design Automation Parser

ALAMEDA, CA--(Marketwired - Aug 13, 2013) - Verific Design Automation (www.verific.com), provider of SystemVerilog, Verilog and VHDL parsers, today announced that Tabula (www.tabula.com) has added ...
Design-Reuse

Synopsys Launches SystemVerilog Catalyst Program

MOUNTAIN VIEW, Calif., October 6, 2003 - Synopsys, Inc. (Nasdaq: SNPS), the world leader in semiconductor design software, today announced its SystemVerilog Catalyst Program. The SystemVerilog ...
Linux Journal

Icarus Verilog: Open-Source Verilog More Than a Year Later

About 16 months ago, in the February 2001 Linux Journal [see www.linuxjournal.com/article/4428], we reviewed the state of open source in electronic design automation ...
EDN

SystemVerilog and ALF standards move forward

Santa Cruz, Calif. – EDA standards efforts eased on several fronts last week, as Cadence Design Systems Inc. said it will support Accellera's SystemVerilog language, and Accellera announced IEEE ...